1. Technical Field
The present invention relates in general to electronic multiplexer (MUX) circuits. Still more particularly, the present invention relates to an improved method and system for wiring efficiency in a permute unit.
2. Description of the Related Art
Permute units are electronic circuits that use multiplexer (MUX) circuits to shuffle one or more data signals (e.g., vectors) between multiple register files in a computer processor, such as a single instruction multiple data (SIMD) “VMX” processor. VMX SIMD processors may include 256-bit vector registers and may be tuned for floating-point and integer instruction sets.
With reference now to FIG. 1, there is depicted a schematic diagram of a permute unit, as utilized in the prior art. Permute unit 2 includes multiplexer (MUX) 0 4, MUX1 5, MUX2 6 and MUX3 7. Each MUX may receive a control signal and one or more data input signals from register file (RF) 0 105, RF1 110, RF2 115, and/or RF3 120. Conventional permute units, such as permute unit 2 which is a 4-way double-precision floating-point SIMD unit, may include more than 512 horizontal wiring tracks or more than 1024 horizontal wiring tracks if inputs come from register bypass busses in addition to the register files. The horizontal wiring tracks function as interconnects between the MUX circuits and also provide control signals to the MUX circuits. However, large numbers of horizontal wiring tracks and long interconnect lengths can impair the overall performance of a permute unit by reducing operating speed and increasing power consumption. Permute units that include large numbers of horizontal wiring tracks also occupy large amounts of physical space, thereby limiting the flexibility of circuit designs by increasing the size of the physical footprint required for the permute unit.